//七段译码器
module decode_7( inbcd,outseven );
    inout [3:0] inbcd; 
    output reg [7:0] outseven;
    always@ ( inbcd )
    begin 
        case ( inbcd )
        4'b0000:outseven = 8'b11000000;
        4'b0001:outseven = 8'b11111001;
        4'b0010:outseven = 8'b10100100;
        4'b0011:outseven = 8'b10110000;
        4'b0100:outseven = 8'b10011001;
        4'b0101:outseven = 8'b10010010;
        4'b0110:outseven = 8'b10000010;
        4'b0111:outseven = 8'b11111000;
        4'b1000:outseven = 8'b10000000;
        4'b1001:outseven = 8'b10010000;
        default:outseven = 8'b01010101;
        endcase
    end 
endmodule
//分频
module dclk(clk,sec);
    input clk;//输入100MHZ时钟信号
    output reg sec;//输出成1HZ的脉冲信号
    integer count;//reg [26:0] 
    always@ ( posedge clk )
    begin
        if (count < 99999999 ) //100000000（100兆）计数器 
            begin
                count = count + 1;
                sec = 0; 
            end
        else 
            begin
                count = 0;
                sec = 1;
            end
    end 
endmodule