#-----------------------------------------------------------
# Vivado v2015.4 (64-bit)
# SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
# IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
# Start of session at: Wed Sep 28 20:12:59 2016
# Process ID: 9152
# Current directory: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent9088 C:\Users\Rongren\GoogleDrive\studyWorks\verilog\verilog_exp\Traffic_lights_sim\Traffic_lights.xpr
# Log file: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/vivado.log
# Journal file: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim\vivado.jou
#-----------------------------------------------------------
start_gui
open_project C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2015.4/data/ip'.
open_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:09 . Memory (MB): peak = 769.656 ; gain = 137.805
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'trafic_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
"xvlog -m64 --relax -prj trafic_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/Hz.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Hz
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/M_to_C.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module M_to_C
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/chooser.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module traffic_lights
INFO: [VRFC 10-2458] undeclared symbol Power, assumed default net type wire [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:55]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module trafic_tb
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v:33]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto dcecd6de03ca414daaab47f1f46dbe8f --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot trafic_tb_behav xil_defaultlib.trafic_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.chooser
Compiling module xil_defaultlib.Hz
Compiling module xil_defaultlib.M_to_C
Compiling module xil_defaultlib.traffic_lights
Compiling module xil_defaultlib.trafic_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot trafic_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xsim.dir/trafic_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Wed Sep 28 20:14:20 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "trafic_tb_behav -key {Behavioral:sim_1:Functional:trafic_tb} -tclbatch {trafic_tb.tcl} -view {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/trafic_tb_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
open_wave_config C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/trafic_tb_behav.wcfg
source trafic_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 10000000ns
$finish called at time : 200 us : File "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" Line 30
INFO: [USF-XSim-96] XSim completed. Design snapshot 'trafic_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 10000000ns
launch_simulation: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 769.793 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
update_compile_order -fileset sim_1
update_compile_order -fileset sim_1
set_property top Hz_tb [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
set_property top Hz [current_fileset]
update_compile_order -fileset sources_1
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'Hz_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
"xvlog -m64 --relax -prj Hz_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/Hz.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Hz
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Hz_tb
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v:69]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto dcecd6de03ca414daaab47f1f46dbe8f --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Hz_tb_behav xil_defaultlib.Hz_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.Hz
Compiling module xil_defaultlib.Hz_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot Hz_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xsim.dir/Hz_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Wed Sep 28 20:15:35 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "Hz_tb_behav -key {Behavioral:sim_1:Functional:Hz_tb} -tclbatch {Hz_tb.tcl} -view {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/trafic_tb_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
open_wave_config C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/trafic_tb_behav.wcfg
WARNING: Simulation object /trafic_tb/clk was not found in the design.
WARNING: Simulation object /trafic_tb/reset was not found in the design.
WARNING: Simulation object /trafic_tb/set was not found in the design.
WARNING: Simulation object /trafic_tb/online was not found in the design.
WARNING: Simulation object /trafic_tb/C_more was not found in the design.
WARNING: Simulation object /trafic_tb/M_more was not found in the design.
WARNING: Simulation object /trafic_tb/PQc was not found in the design.
WARNING: Simulation object /trafic_tb/PQm was not found in the design.
WARNING: Simulation object /trafic_tb/C_noCar was not found in the design.
WARNING: Simulation object /trafic_tb/M_noCar was not found in the design.
WARNING: Simulation object /trafic_tb/out_num was not found in the design.
WARNING: Simulation object /trafic_tb/R_light was not found in the design.
WARNING: Simulation object /trafic_tb/G_light was not found in the design.
WARNING: Simulation object /trafic_tb/Y_light was not found in the design.
WARNING: Simulation object /trafic_tb/R_light_c was not found in the design.
WARNING: Simulation object /trafic_tb/G_light_c was not found in the design.
WARNING: Simulation object /trafic_tb/Y_light_c was not found in the design.
WARNING: Simulation object /trafic_tb/DUT/hhz/sec2 was not found in the design.
source Hz_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 10000000ns
$finish called at time : 10 us : File "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" Line 66
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Hz_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 10000000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 782.828 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
set_property top traffic_lights [current_fileset]
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
update_compile_order -fileset sim_1
update_compile_order -fileset sim_1
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'traffic_lights' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
"xvlog -m64 --relax -prj traffic_lights_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/M_to_C.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module M_to_C
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/chooser.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/Hz.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Hz
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module traffic_lights
INFO: [VRFC 10-2458] undeclared symbol Power, assumed default net type wire [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:55]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto dcecd6de03ca414daaab47f1f46dbe8f --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot traffic_lights_behav xil_defaultlib.traffic_lights xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.chooser
Compiling module xil_defaultlib.Hz
Compiling module xil_defaultlib.M_to_C
Compiling module xil_defaultlib.traffic_lights
Compiling module xil_defaultlib.glbl
Built simulation snapshot traffic_lights_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xsim.dir/traffic_lights_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Wed Sep 28 22:53:59 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "traffic_lights_behav -key {Behavioral:sim_1:Functional:traffic_lights} -tclbatch {traffic_lights.tcl} -view {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/trafic_tb_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
open_wave_config C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/trafic_tb_behav.wcfg
WARNING: Simulation object /trafic_tb/clk was not found in the design.
WARNING: Simulation object /trafic_tb/reset was not found in the design.
WARNING: Simulation object /trafic_tb/set was not found in the design.
WARNING: Simulation object /trafic_tb/online was not found in the design.
WARNING: Simulation object /trafic_tb/C_more was not found in the design.
WARNING: Simulation object /trafic_tb/M_more was not found in the design.
WARNING: Simulation object /trafic_tb/PQc was not found in the design.
WARNING: Simulation object /trafic_tb/PQm was not found in the design.
WARNING: Simulation object /trafic_tb/C_noCar was not found in the design.
WARNING: Simulation object /trafic_tb/M_noCar was not found in the design.
WARNING: Simulation object /trafic_tb/out_num was not found in the design.
WARNING: Simulation object /trafic_tb/R_light was not found in the design.
WARNING: Simulation object /trafic_tb/G_light was not found in the design.
WARNING: Simulation object /trafic_tb/Y_light was not found in the design.
WARNING: Simulation object /trafic_tb/R_light_c was not found in the design.
WARNING: Simulation object /trafic_tb/G_light_c was not found in the design.
WARNING: Simulation object /trafic_tb/Y_light_c was not found in the design.
WARNING: Simulation object /trafic_tb/DUT/hhz/sec2 was not found in the design.
source traffic_lights.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 10000000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'traffic_lights_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 10000000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 801.188 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
close_project
****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.hw/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Wed Sep 28 22:56:27 2016...
create_project sim_md C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md -part xc7a100tcsg324-1
INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
Current project path is 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md'
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2015.4/data/ip'.
file mkdir C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sources_1/new
close [ open C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sources_1/new/Hz.v w ]
add_files C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sources_1/new/Hz.v
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
file mkdir C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v w ]
add_files -fileset sim_1 C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v
update_compile_order -fileset sim_1
update_compile_order -fileset sim_1
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'Hz_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
"xvlog -m64 --relax -prj Hz_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sources_1/new/Hz.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Hz
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Hz_tb
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:32]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto 6fa0c02f09bf4e8d8941b425dde972b8 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Hz_tb_behav xil_defaultlib.Hz_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.Hz
Compiling module xil_defaultlib.Hz_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot Hz_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/xsim.dir/Hz_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Wed Sep 28 22:59:17 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "Hz_tb_behav -key {Behavioral:sim_1:Functional:Hz_tb} -tclbatch {Hz_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
source Hz_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Hz_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 834.695 ; gain = 0.000
update_compile_order -fileset sim_1
set_property -name {xsim.simulate.runtime} -value {1000000ns} -objects [current_fileset -simset]
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'Hz_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
"xvlog -m64 --relax -prj Hz_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sources_1/new/Hz.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Hz
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Hz_tb
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:32]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto 6fa0c02f09bf4e8d8941b425dde972b8 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Hz_tb_behav xil_defaultlib.Hz_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.Hz
Compiling module xil_defaultlib.Hz_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot Hz_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/xsim.dir/Hz_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Wed Sep 28 23:00:16 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "Hz_tb_behav -key {Behavioral:sim_1:Functional:Hz_tb} -tclbatch {Hz_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
source Hz_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000000ns
$finish called at time : 10 us : File "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v" Line 29
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Hz_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 834.695 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'chooser_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
"xvlog -m64 --relax -prj chooser_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sources_1/new/Hz.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser_tb
INFO: [VRFC 10-2458] undeclared symbol sec, assumed default net type wire [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:30]
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:35]
ERROR: [VRFC 10-1412] syntax error near = [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:35]
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:38]
ERROR: [VRFC 10-1040] module chooser_tb ignored due to previous errors [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:23]
INFO: [USF-XSim-99] Step results log file:'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/xvlog.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/xvlog.log' file for more information.
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'chooser_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
"xvlog -m64 --relax -prj chooser_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sources_1/new/Hz.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser_tb
INFO: [VRFC 10-2458] undeclared symbol sec, assumed default net type wire [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:30]
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:35]
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:38]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto 6fa0c02f09bf4e8d8941b425dde972b8 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot chooser_tb_behav xil_defaultlib.chooser_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.chooser
Compiling module xil_defaultlib.chooser_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot chooser_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/xsim.dir/chooser_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Wed Sep 28 23:37:46 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "chooser_tb_behav -key {Behavioral:sim_1:Functional:chooser_tb} -tclbatch {chooser_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
source chooser_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000000ns
$finish called at time : 10 us : File "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v" Line 32
INFO: [USF-XSim-96] XSim completed. Design snapshot 'chooser_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 841.383 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'chooser_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
"xvlog -m64 --relax -prj chooser_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sources_1/new/Hz.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser_tb
INFO: [VRFC 10-2458] undeclared symbol sec, assumed default net type wire [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:30]
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:35]
ERROR: [VRFC 10-1412] syntax error near = [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:35]
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:38]
ERROR: [VRFC 10-1040] module chooser_tb ignored due to previous errors [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:23]
INFO: [USF-XSim-99] Step results log file:'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/xvlog.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/xvlog.log' file for more information.
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'chooser_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
"xvlog -m64 --relax -prj chooser_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sources_1/new/Hz.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser_tb
INFO: [VRFC 10-2458] undeclared symbol sec, assumed default net type wire [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:30]
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:35]
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:38]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto 6fa0c02f09bf4e8d8941b425dde972b8 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot chooser_tb_behav xil_defaultlib.chooser_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.chooser
Compiling module xil_defaultlib.chooser_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot chooser_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/xsim.dir/chooser_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Wed Sep 28 23:44:29 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "chooser_tb_behav -key {Behavioral:sim_1:Functional:chooser_tb} -tclbatch {chooser_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
source chooser_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000000ns
$finish called at time : 10 us : File "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v" Line 32
INFO: [USF-XSim-96] XSim completed. Design snapshot 'chooser_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 847.836 ; gain = 0.000
save_wave_config {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/chooser_tb_behav.wcfg}
add_files -fileset sim_1 -norecurse C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/chooser_tb_behav.wcfg
set_property xsim.view C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/chooser_tb_behav.wcfg [get_filesets sim_1]
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'chooser_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
"xvlog -m64 --relax -prj chooser_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sources_1/new/Hz.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser_tb
INFO: [VRFC 10-2458] undeclared symbol sec, assumed default net type wire [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:30]
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:35]
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:38]
ERROR: [VRFC 10-1412] syntax error near # [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:47]
ERROR: [VRFC 10-1040] module chooser_tb ignored due to previous errors [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:23]
INFO: [USF-XSim-99] Step results log file:'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/xvlog.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/xvlog.log' file for more information.
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'chooser_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
"xvlog -m64 --relax -prj chooser_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sources_1/new/Hz.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser_tb
INFO: [VRFC 10-2458] undeclared symbol sec, assumed default net type wire [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:30]
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:35]
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:38]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto 6fa0c02f09bf4e8d8941b425dde972b8 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot chooser_tb_behav xil_defaultlib.chooser_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.chooser
Compiling module xil_defaultlib.chooser_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot chooser_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/xsim.dir/chooser_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Wed Sep 28 23:50:04 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "chooser_tb_behav -key {Behavioral:sim_1:Functional:chooser_tb} -tclbatch {chooser_tb.tcl} -view {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/chooser_tb_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
open_wave_config C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/chooser_tb_behav.wcfg
source chooser_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000000ns
$finish called at time : 10 us : File "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v" Line 32
INFO: [USF-XSim-96] XSim completed. Design snapshot 'chooser_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000000ns
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 848.820 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'chooser_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
"xvlog -m64 --relax -prj chooser_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sources_1/new/Hz.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser_tb
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:35]
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v:38]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto 6fa0c02f09bf4e8d8941b425dde972b8 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot chooser_tb_behav xil_defaultlib.chooser_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.chooser
Compiling module xil_defaultlib.chooser_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot chooser_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav/xsim.dir/chooser_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Wed Sep 28 23:54:48 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "chooser_tb_behav -key {Behavioral:sim_1:Functional:chooser_tb} -tclbatch {chooser_tb.tcl} -view {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/chooser_tb_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
open_wave_config C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/chooser_tb_behav.wcfg
source chooser_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000000ns
$finish called at time : 10 us : File "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/sim_md/sim_md.srcs/sim_1/new/Hz_tb.v" Line 32
INFO: [USF-XSim-96] XSim completed. Design snapshot 'chooser_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 849.684 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
exit
INFO: [Common 17-206] Exiting Vivado at Thu Sep 29 00:31:05 2016...