#----------------------------------------------------------- # Vivado v2015.4 (64-bit) # SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015 # IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 # Start of session at: Mon Sep 26 08:29:43 2016 # Process ID: 4136 # Current directory: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent4712 C:\Users\Rongren\GoogleDrive\studyWorks\verilog\verilog_exp\Traffic_lights\Traffic_lights.xpr # Log file: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/vivado.log # Journal file: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights\vivado.jou #----------------------------------------------------------- start_gui open_project C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.xpr Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2015.4/data/ip'. open_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 700.816 ; gain = 100.762 update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 file mkdir C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.srcs/constrs_1 file mkdir C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.srcs/constrs_1/new WARNING: [filemgmt 20-342] File / dir doesn't exist, skipping: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.srcs/constrs_1/new/traffic.xdc close [ open C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.srcs/constrs_1/new/traffic.xdc w ] add_files -fileset constrs_1 C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.srcs/constrs_1/new/traffic.xdc launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 08:54:33 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 08:54:34 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 08:55:33 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 08:55:33 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 08:57:35 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 08:57:35 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 09:02:32 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 09:02:32 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 09:03:04 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 09:03:04 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 09:07:47 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 09:07:47 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log open_hw connect_hw_server INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 INFO: [Labtools 27-2222] Launching hw_server... INFO: [Labtools 27-2221] Launch Output: ****** Xilinx hw_server v2015.4 **** Build date : Nov 17 2015-18:01:07 ** Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved. connect_hw_server: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 825.551 ; gain = 0.000 open_hw_target INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210274533488A set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] current_hw_device [lindex [get_hw_devices] 0] refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH program_hw_devices: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 825.551 ; gain = 0.000 refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 09:20:11 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 09:20:11 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 09:24:04 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 09:24:04 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 09:28:39 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 09:28:39 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 09:33:22 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 09:33:22 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH program_hw_devices: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 861.242 ; gain = 0.000 refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 09:39:11 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 09:39:11 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 09:45:54 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 09:45:54 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 09:52:37 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 09:52:37 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 10:01:54 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 10:01:54 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 10:08:27 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 10:08:27 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 10:09:24 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 10:09:24 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 10:12:36 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 10:12:36 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 10:20:00 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 10:20:00 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 10:24:03 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 10:24:03 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run impl_1 -prev_step launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 10:29:31 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 10:34:02 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 10:34:02 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH program_hw_devices: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 866.148 ; gain = 0.000 refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 10:38:32 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 10:38:32 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 10:43:17 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 10:43:17 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run impl_1 -prev_step launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 10:47:34 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 10:51:06 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 10:51:06 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run impl_1 -prev_step launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 10:56:45 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 11:02:46 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 11:02:46 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 11:15:04 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 11:15:04 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 11:20:15 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 11:20:15 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 11:23:58 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 11:23:58 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log reset_run impl_1 -prev_step reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 11:27:05 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 11:27:05 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 11:34:41 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 11:34:41 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Mon Sep 26 11:39:08 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log [Mon Sep 26 11:39:08 2016] Launched impl_1... Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210274533488A exit INFO: [Common 17-206] Exiting Vivado at Mon Sep 26 11:43:59 2016...