#-----------------------------------------------------------
# Vivado v2015.4 (64-bit)
# SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
# IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
# Start of session at: Tue Sep 27 08:17:04 2016
# Process ID: 6256
# Current directory: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent5076 C:\Users\Rongren\GoogleDrive\studyWorks\verilog\verilog_exp\Traffic_lights_sim\Traffic_lights.xpr
# Log file: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/vivado.log
# Journal file: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim\vivado.jou
#-----------------------------------------------------------
start_gui
open_project C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.xpr
INFO: [Project 1-313] Project file moved from 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights' since last save.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2015.4/data/ip'.
open_project: Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 757.426 ; gain = 152.672
update_compile_order -fileset sources_1
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'trafic_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
"xvlog -m64 --relax -prj trafic_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/M_to_C.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module M_to_C
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/chooser.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module traffic_lights
INFO: [VRFC 10-2458] undeclared symbol flash, assumed default net type wire [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:45]
ERROR: [VRFC 10-2109] no definition for port out_num [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:23]
WARNING: [VRFC 10-2379] empty port in module declaration [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:23]
ERROR: [VRFC 10-1040] module traffic_lights ignored due to previous errors [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:23]
INFO: [USF-XSim-99] Step results log file:'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xvlog.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xvlog.log' file for more information.
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'trafic_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
"xvlog -m64 --relax -prj trafic_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/M_to_C.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module M_to_C
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/chooser.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module traffic_lights
INFO: [VRFC 10-2458] undeclared symbol flash, assumed default net type wire [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:46]
WARNING: [VRFC 10-2379] empty port in module declaration [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:23]
ERROR: [VRFC 10-1241] port R_counter is not defined [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:28]
ERROR: [VRFC 10-1241] port Y_counter is not defined [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:29]
ERROR: [VRFC 10-1040] module traffic_lights ignored due to previous errors [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:23]
INFO: [USF-XSim-99] Step results log file:'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xvlog.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xvlog.log' file for more information.
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'trafic_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
"xvlog -m64 --relax -prj trafic_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/M_to_C.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module M_to_C
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/chooser.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module traffic_lights
INFO: [VRFC 10-2458] undeclared symbol flash, assumed default net type wire [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:46]
WARNING: [VRFC 10-2379] empty port in module declaration [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:23]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module trafic_tb
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v:34]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto dcecd6de03ca414daaab47f1f46dbe8f --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot trafic_tb_behav xil_defaultlib.trafic_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.chooser
Compiling module xil_defaultlib.M_to_C
Compiling module xil_defaultlib.traffic_lights
Compiling module xil_defaultlib.trafic_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot trafic_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xsim.dir/trafic_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Tue Sep 27 08:41:27 2016...
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:09 . Memory (MB): peak = 767.547 ; gain = 0.000
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "trafic_tb_behav -key {Behavioral:sim_1:Functional:trafic_tb} -tclbatch {trafic_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
source trafic_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
$finish called at time : 1 us : File "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" Line 31
INFO: [USF-XSim-96] XSim completed. Design snapshot 'trafic_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 771.027 ; gain = 3.480
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'trafic_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
"xvlog -m64 --relax -prj trafic_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/M_to_C.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module M_to_C
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/chooser.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module traffic_lights
WARNING: [VRFC 10-2379] empty port in module declaration [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:23]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module trafic_tb
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v:34]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto dcecd6de03ca414daaab47f1f46dbe8f --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot trafic_tb_behav xil_defaultlib.trafic_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.chooser
Compiling module xil_defaultlib.M_to_C
Compiling module xil_defaultlib.traffic_lights
Compiling module xil_defaultlib.trafic_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot trafic_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xsim.dir/trafic_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Tue Sep 27 08:44:03 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "trafic_tb_behav -key {Behavioral:sim_1:Functional:trafic_tb} -tclbatch {trafic_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
source trafic_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
$finish called at time : 1 us : File "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" Line 31
INFO: [USF-XSim-96] XSim completed. Design snapshot 'trafic_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 773.402 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'trafic_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
"xvlog -m64 --relax -prj trafic_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/M_to_C.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module M_to_C
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/chooser.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module traffic_lights
WARNING: [VRFC 10-2379] empty port in module declaration [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:23]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module trafic_tb
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v:34]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto dcecd6de03ca414daaab47f1f46dbe8f --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot trafic_tb_behav xil_defaultlib.trafic_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.chooser
Compiling module xil_defaultlib.M_to_C
Compiling module xil_defaultlib.traffic_lights
Compiling module xil_defaultlib.trafic_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot trafic_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xsim.dir/trafic_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Tue Sep 27 08:48:33 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "trafic_tb_behav -key {Behavioral:sim_1:Functional:trafic_tb} -tclbatch {trafic_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
source trafic_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
$finish called at time : 1 us : File "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" Line 31
INFO: [USF-XSim-96] XSim completed. Design snapshot 'trafic_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 784.992 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'trafic_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
"xvlog -m64 --relax -prj trafic_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/M_to_C.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module M_to_C
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/chooser.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module traffic_lights
WARNING: [VRFC 10-2379] empty port in module declaration [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:23]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module trafic_tb
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v:34]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto dcecd6de03ca414daaab47f1f46dbe8f --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot trafic_tb_behav xil_defaultlib.trafic_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.chooser
Compiling module xil_defaultlib.M_to_C
Compiling module xil_defaultlib.traffic_lights
Compiling module xil_defaultlib.trafic_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot trafic_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xsim.dir/trafic_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Tue Sep 27 09:49:25 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "trafic_tb_behav -key {Behavioral:sim_1:Functional:trafic_tb} -tclbatch {trafic_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
source trafic_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
$finish called at time : 1 us : File "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" Line 31
INFO: [USF-XSim-96] XSim completed. Design snapshot 'trafic_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 784.992 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'trafic_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
"xvlog -m64 --relax -prj trafic_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/M_to_C.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module M_to_C
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/chooser.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module traffic_lights
WARNING: [VRFC 10-2379] empty port in module declaration [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:23]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module trafic_tb
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v:34]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto dcecd6de03ca414daaab47f1f46dbe8f --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot trafic_tb_behav xil_defaultlib.trafic_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.chooser
Compiling module xil_defaultlib.M_to_C
Compiling module xil_defaultlib.traffic_lights
Compiling module xil_defaultlib.trafic_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot trafic_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xsim.dir/trafic_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Tue Sep 27 09:54:44 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "trafic_tb_behav -key {Behavioral:sim_1:Functional:trafic_tb} -tclbatch {trafic_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
source trafic_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
$finish called at time : 1 us : File "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" Line 31
INFO: [USF-XSim-96] XSim completed. Design snapshot 'trafic_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 784.992 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'trafic_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
"xvlog -m64 --relax -prj trafic_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/M_to_C.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module M_to_C
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/chooser.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module traffic_lights
WARNING: [VRFC 10-2379] empty port in module declaration [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:23]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module trafic_tb
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v:34]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto dcecd6de03ca414daaab47f1f46dbe8f --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot trafic_tb_behav xil_defaultlib.trafic_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.chooser
Compiling module xil_defaultlib.M_to_C
Compiling module xil_defaultlib.traffic_lights
Compiling module xil_defaultlib.trafic_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot trafic_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xsim.dir/trafic_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Tue Sep 27 09:56:41 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "trafic_tb_behav -key {Behavioral:sim_1:Functional:trafic_tb} -tclbatch {trafic_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
source trafic_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
$finish called at time : 1 us : File "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" Line 31
INFO: [USF-XSim-96] XSim completed. Design snapshot 'trafic_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 784.992 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'trafic_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
"xvlog -m64 --relax -prj trafic_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/M_to_C.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module M_to_C
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/chooser.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module traffic_lights
WARNING: [VRFC 10-2379] empty port in module declaration [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:23]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module trafic_tb
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v:34]
ERROR: [VRFC 10-1412] syntax error near ï [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v:44]
ERROR: [VRFC 10-1040] module trafic_tb ignored due to previous errors [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v:23]
INFO: [USF-XSim-99] Step results log file:'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xvlog.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xvlog.log' file for more information.
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'trafic_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
"xvlog -m64 --relax -prj trafic_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/M_to_C.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module M_to_C
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/chooser.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module traffic_lights
WARNING: [VRFC 10-2379] empty port in module declaration [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:23]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module trafic_tb
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v:34]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto dcecd6de03ca414daaab47f1f46dbe8f --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot trafic_tb_behav xil_defaultlib.trafic_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.chooser
Compiling module xil_defaultlib.M_to_C
Compiling module xil_defaultlib.traffic_lights
Compiling module xil_defaultlib.trafic_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot trafic_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xsim.dir/trafic_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Tue Sep 27 09:59:16 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "trafic_tb_behav -key {Behavioral:sim_1:Functional:trafic_tb} -tclbatch {trafic_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
source trafic_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
$finish called at time : 1 us : File "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" Line 31
INFO: [USF-XSim-96] XSim completed. Design snapshot 'trafic_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 784.992 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'trafic_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
"xvlog -m64 --relax -prj trafic_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/M_to_C.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module M_to_C
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/chooser.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module traffic_lights
WARNING: [VRFC 10-2379] empty port in module declaration [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:23]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module trafic_tb
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v:34]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto dcecd6de03ca414daaab47f1f46dbe8f --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot trafic_tb_behav xil_defaultlib.trafic_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.chooser
Compiling module xil_defaultlib.M_to_C
Compiling module xil_defaultlib.traffic_lights
Compiling module xil_defaultlib.trafic_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot trafic_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xsim.dir/trafic_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Tue Sep 27 10:14:29 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "trafic_tb_behav -key {Behavioral:sim_1:Functional:trafic_tb} -tclbatch {trafic_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
source trafic_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'trafic_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 803.785 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'trafic_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
"xvlog -m64 --relax -prj trafic_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/M_to_C.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module M_to_C
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/chooser.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module traffic_lights
WARNING: [VRFC 10-2379] empty port in module declaration [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:23]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module trafic_tb
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v:34]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto dcecd6de03ca414daaab47f1f46dbe8f --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot trafic_tb_behav xil_defaultlib.trafic_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.chooser
Compiling module xil_defaultlib.M_to_C
Compiling module xil_defaultlib.traffic_lights
Compiling module xil_defaultlib.trafic_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot trafic_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xsim.dir/trafic_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Tue Sep 27 10:16:24 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "trafic_tb_behav -key {Behavioral:sim_1:Functional:trafic_tb} -tclbatch {trafic_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
source trafic_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'trafic_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 803.785 ; gain = 0.000
set_property -name {xsim.simulate.runtime} -value {10000ns} -objects [current_fileset -simset]
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'trafic_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
"xvlog -m64 --relax -prj trafic_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/M_to_C.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module M_to_C
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/chooser.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module chooser
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module traffic_lights
WARNING: [VRFC 10-2379] empty port in module declaration [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sources_1/new/traffic_lights.v:23]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module trafic_tb
WARNING: [VRFC 10-607] empty loop variable assignment statement violates IEEE 1800 syntax [C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v:34]
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto dcecd6de03ca414daaab47f1f46dbe8f --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot trafic_tb_behav xil_defaultlib.trafic_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.chooser
Compiling module xil_defaultlib.M_to_C
Compiling module xil_defaultlib.traffic_lights
Compiling module xil_defaultlib.trafic_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot trafic_tb_behav

****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav/xsim.dir/trafic_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Tue Sep 27 10:17:19 2016...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "trafic_tb_behav -key {Behavioral:sim_1:Functional:trafic_tb} -tclbatch {trafic_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
Time resolution is 1 ps
source trafic_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 10000ns
$finish called at time : 1500 ns : File "C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.srcs/sim_1/new/trafic_tb.v" Line 31
INFO: [USF-XSim-96] XSim completed. Design snapshot 'trafic_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 10000ns
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 843.348 ; gain = 0.000
open_project C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2015.4/data/ip'.
open_project: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 843.348 ; gain = 0.000
current_project Traffic_lights
close_sim
INFO: [Simtcl 6-16] Simulation closed
close_project
****** Webtalk v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights_sim/Traffic_lights.hw/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Tue Sep 27 16:03:14 2016...
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2015.4
  **** Build date : Nov 17 2015-18:01:07
    ** Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.


open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210274533488A
set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0]
current_hw_device [lindex [get_hw_devices] 0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
set_property PROBES.FILE {} [lindex [get_hw_devices] 0]
set_property PROGRAM.FILE {C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/traffic_lights.bit} [lindex [get_hw_devices] 0]
program_hw_devices [lindex [get_hw_devices] 0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210274533488A
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream
[Tue Sep 27 18:33:34 2016] Launched synth_1...
Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log
[Tue Sep 27 18:33:34 2016] Launched impl_1...
Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream
[Tue Sep 27 18:34:38 2016] Launched synth_1...
Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/synth_1/runme.log
[Tue Sep 27 18:34:38 2016] Launched impl_1...
Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log
reset_run impl_1
launch_runs impl_1 -to_step write_bitstream
[Tue Sep 27 18:38:46 2016] Launched impl_1...
Run output will be captured here: C:/Users/Rongren/GoogleDrive/studyWorks/verilog/verilog_exp/Traffic_lights/Traffic_lights.runs/impl_1/runme.log
exit
INFO: [Common 17-206] Exiting Vivado at Tue Sep 27 18:39:49 2016...