#-----------------------------------------------------------
# Vivado v2015.2 (64-bit)
# SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
# IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
# Start of session at: Sat Sep 24 15:08:50 2016
# Process ID: 2288
# Log file: C:/Users/Administrator/Desktop/clock/vivado.log
# Journal file: C:/Users/Administrator/Desktop/clock\vivado.jou
#-----------------------------------------------------------
start_gui
open_project C:/Users/Administrator/Desktop/clock/clock.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2015.2/data/ip'.
open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 723.492 ; gain = 145.246
reset_run impl_1 -prev_step 
launch_runs impl_1 -to_step write_bitstream
[Sat Sep 24 15:09:53 2016] Launched impl_1...
Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2015.2
  **** Build date : Jun 26 2015-16:56:39
    ** Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.


open_hw_target [lindex [get_hw_targets -of_objects [get_hw_servers localhost]] 0]
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210274533488A
set_property PROGRAM.FILE {C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/clock.bit} [lindex [get_hw_devices] 0]
current_hw_device [lindex [get_hw_devices] 0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
set_property PROBES.FILE {} [lindex [get_hw_devices] 0]
set_property PROGRAM.FILE {C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/clock.bit} [lindex [get_hw_devices] 0]
program_hw_devices [lindex [get_hw_devices] 0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream
[Sat Sep 24 15:11:44 2016] Launched synth_1...
Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log
[Sat Sep 24 15:11:44 2016] Launched impl_1...
Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log
set_property PROBES.FILE {} [lindex [get_hw_devices] 0]
set_property PROGRAM.FILE {C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/clock.bit} [lindex [get_hw_devices] 0]
program_hw_devices [lindex [get_hw_devices] 0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
****** Webtalk v2015.2 (64-bit)
  **** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
  **** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Administrator/Desktop/clock/clock.hw/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-186] 'C:/Users/Administrator/Desktop/clock/clock.hw/webtalk/usage_statistics_ext_labtool.xml' has been successfully sent to Xilinx on Sat Sep 24 17:34:38 2016. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2015.2/doc/webtalk_introduction.html.
webtalk_transmit: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 57.852 ; gain = 0.031
INFO: [Common 17-206] Exiting Webtalk at Sat Sep 24 17:34:38 2016...
exit
INFO: [Common 17-206] Exiting Vivado at Sat Sep 24 17:34:40 2016...