#----------------------------------------------------------- # Vivado v2015.2 (64-bit) # SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015 # IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015 # Start of session at: Sat Sep 24 08:37:36 2016 # Process ID: 3596 # Log file: C:/Users/Administrator/Desktop/clock/vivado.log # Journal file: C:/Users/Administrator/Desktop/clock\vivado.jou #----------------------------------------------------------- start_gui open_project C:/Users/Administrator/Desktop/clock/clock.xpr Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2015.2/data/ip'. open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 734.387 ; gain = 158.855 reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 09:10:14 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 09:10:14 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 09:11:31 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 09:11:31 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 09:12:27 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 09:12:27 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 09:13:41 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 09:13:41 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 09:14:58 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 09:14:58 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 09:17:18 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 09:17:18 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 09:18:22 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 09:18:22 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 09:22:37 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 09:22:37 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log open_hw connect_hw_server INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 INFO: [Labtools 27-2222] Launching hw_server... INFO: [Labtools 27-2221] Launch Output: ****** Xilinx hw_server v2015.2 **** Build date : Jun 26 2015-16:56:39 ** Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved. open_hw_target [lindex [get_hw_targets -of_objects [get_hw_servers localhost]] 0] INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210274533488A set_property PROGRAM.FILE {C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/clock.bit} [lindex [get_hw_devices] 0] current_hw_device [lindex [get_hw_devices] 0] refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/clock.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 09:32:28 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 09:32:28 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 09:33:18 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 09:33:18 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 09:33:40 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 09:33:40 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/clock.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 10:09:26 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 10:09:26 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 10:12:18 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 10:12:18 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log open_run impl_1 INFO: [Netlist 29-17] Analyzing 50 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2015.2 INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [C:/Users/Administrator/Desktop/clock/.Xil/Vivado-3596-admin63/dcp/clock.xdc] Finished Parsing XDC File [C:/Users/Administrator/Desktop/clock/.Xil/Vivado-3596-admin63/dcp/clock.xdc] Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.140 . Memory (MB): peak = 1026.184 ; gain = 0.000 Restored from archive | CPU: 1.000000 secs | Memory: 0.000000 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.140 . Memory (MB): peak = 1026.184 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-41] Interrupt caught. Command should exit soon. open_run: Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1155.785 ; gain = 256.031 INFO: [Common 17-344] 'open_run' was cancelled WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. close_design set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/clock.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 10:18:02 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 10:18:02 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log reset_run impl_1 -noclean_dir reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 10:18:56 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 10:18:56 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 10:57:44 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 10:57:44 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 10:58:15 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 10:58:15 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 10:58:44 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 10:58:44 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/clock.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 11:07:01 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 11:07:01 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 11:09:29 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 11:09:29 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/clock.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 11:16:01 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 11:16:01 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/clock.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. reset_run synth_1 launch_runs impl_1 -to_step write_bitstream [Sat Sep 24 11:25:00 2016] Launched synth_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/synth_1/runme.log [Sat Sep 24 11:25:00 2016] Launched impl_1... Run output will be captured here: C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/runme.log set_property PROBES.FILE {} [lindex [get_hw_devices] 0] set_property PROGRAM.FILE {C:/Users/Administrator/Desktop/clock/clock.runs/impl_1/clock.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-3164] End of startup status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. exit INFO: [Common 17-206] Exiting Vivado at Sat Sep 24 11:29:05 2016...