#-----------------------------------------------------------
# Vivado v2015.2 (64-bit)
# SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
# IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
# Start of session at: Mon Sep 26 20:11:43 2016
# Process ID: 304
# Log file: C:/Users/Administrator/Desktop/clock/vivado.log
# Journal file: C:/Users/Administrator/Desktop/clock\vivado.jou
#-----------------------------------------------------------
start_gui
open_project C:/Users/Administrator/Desktop/clock/clock.xpr
INFO: [Project 1-313] Project file moved from 'E:/clock' since last save.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2015.2/data/ip'.
open_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 709.828 ; gain = 134.813
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'clock_td' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'C:/Users/Administrator/Desktop/clock/clock.sim/sim_1/behav'
"xvlog -m64 --relax -prj clock_td_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Administrator/Desktop/clock/clock.srcs/sources_1/new/clock.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module clock
INFO: [VRFC 10-311] analyzing module clock24
INFO: [VRFC 10-311] analyzing module clock60
INFO: [VRFC 10-311] analyzing module dclk
INFO: [VRFC 10-311] analyzing module dclk1000HZ
INFO: [VRFC 10-311] analyzing module ring
INFO: [VRFC 10-311] analyzing module decode_7
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Administrator/Desktop/clock/clock.srcs/sim_1/new/clock_td.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module clock_td
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Administrator/Desktop/clock/clock.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Administrator/Desktop/clock/clock.sim/sim_1/behav'
Vivado Simulator 2015.2
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.2/bin/unwrapped/win64.o/xelab.exe -wto 7ac463d930a54a5fbf4c88ca44d04d4c --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot clock_td_behav xil_defaultlib.clock_td xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.dclk1000HZ
Compiling module xil_defaultlib.dclk
Compiling module xil_defaultlib.ring
Compiling module xil_defaultlib.clock60
Compiling module xil_defaultlib.clock24
Compiling module xil_defaultlib.decode_7
Compiling module xil_defaultlib.clock
Compiling module xil_defaultlib.clock_td
Compiling module xil_defaultlib.glbl
Waiting for 2 sub-compilation(s) to finish...
Built simulation snapshot clock_td_behav

****** Webtalk v2015.2 (64-bit)
  **** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
  **** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source C:/Users/Administrator/Desktop/clock/clock.sim/sim_1/behav/xsim.dir/clock_td_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] 'C:/Users/Administrator/Desktop/clock/clock.sim/sim_1/behav/xsim.dir/clock_td_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Mon Sep 26 20:22:06 2016. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2015.2/doc/webtalk_introduction.html.
webtalk_transmit: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 58.613 ; gain = 0.059
INFO: [Common 17-206] Exiting Webtalk at Mon Sep 26 20:22:06 2016...
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:10 . Memory (MB): peak = 717.184 ; gain = 0.000
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Administrator/Desktop/clock/clock.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "clock_td_behav -key {Behavioral:sim_1:Functional:clock_td} -tclbatch {clock_td.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.2
Time resolution is 1 ps
source clock_td.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'clock_td_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:15 . Memory (MB): peak = 728.141 ; gain = 10.957
close_sim
INFO: [Simtcl 6-16] Simulation closed
close_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 765.285 ; gain = 0.000
exit
INFO: [Common 17-206] Exiting Vivado at Mon Sep 26 21:37:39 2016...