#----------------------------------------------------------- # Vivado v2015.4 (64-bit) # SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015 # IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 # Start of session at: Tue Jun 07 00:27:43 2016 # Process ID: 6596 # Current directory: C:/Users/Rongren/Downloads/verilog_exp/exp4_2 # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent8608 C:\Users\Rongren\Downloads\verilog_exp\exp4_2\exp_2.xpr # Log file: C:/Users/Rongren/Downloads/verilog_exp/exp4_2/vivado.log # Journal file: C:/Users/Rongren/Downloads/verilog_exp/exp4_2\vivado.jou #----------------------------------------------------------- start_gui open_project C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.xpr INFO: [Project 1-313] Project file moved from 'C:/Users/Rongren/Downloads/verilog_exp/exp_2' since last save. Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2015.4/data/ip'. open_project: Time (s): cpu = 00:00:15 ; elapsed = 00:00:07 . Memory (MB): peak = 777.973 ; gain = 132.199 synth_design -rtl -name rtl_1 Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xc7a100tcsg324-1 Top: latch ERROR: [Synth 8-2671] single value range is not allowed in this mode of verilog [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:44] INFO: [Synth 8-2350] module Memory ignored due to previous errors [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:39] INFO: [Synth 8-2350] module mux2t1 ignored due to previous errors [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:56] INFO: [Synth 8-2350] module Register ignored due to previous errors [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:69] INFO: [Synth 8-2350] module alu_cir ignored due to previous errors [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:79] INFO: [Synth 8-2350] module CMPer ignored due to previous errors [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:88] Failed to read verilog 'C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v' 5 Infos, 0 Warnings, 0 Critical Warnings and 2 Errors encountered. synth_design failed ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details launch_runs synth_1 INFO: [HDL 9-2216] Analyzing Verilog file "C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v" into library work [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:1] [Tue Jun 07 10:51:04 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.runs/synth_1/runme.log reset_run synth_1 launch_runs synth_1 INFO: [HDL 9-2216] Analyzing Verilog file "C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v" into library work [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:1] [Tue Jun 07 10:57:34 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.runs/synth_1/runme.log synth_design -rtl -name rtl_1 Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xc7a100tcsg324-1 Top: latch --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:02:14 ; elapsed = 10:30:29 . Memory (MB): peak = 840.574 ; gain = 669.941 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'latch' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:23] Parameter WIDTH bound to: 8 - type: integer Parameter NUM bound to: 256 - type: integer INFO: [Synth 8-638] synthesizing module 'alu_cir' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:79] Parameter ALU_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'alu_cir' (1#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:79] INFO: [Synth 8-638] synthesizing module 'mux2t1' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:56] Parameter MUX_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'mux2t1' (2#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:56] INFO: [Synth 8-638] synthesizing module 'Register' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:69] Parameter R_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'Register' (3#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:69] INFO: [Synth 8-638] synthesizing module 'Memory' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:39] Parameter M_WIDTH bound to: 8 - type: integer Parameter M_HEIGHT bound to: 256 - type: integer INFO: [Synth 8-256] done synthesizing module 'Memory' (4#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:39] WARNING: [Synth 8-3848] Net NEXT_ZERO in module/entity latch does not have driver. [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:27] INFO: [Synth 8-256] done synthesizing module 'latch' (5#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:23] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:02:16 ; elapsed = 10:30:30 . Memory (MB): peak = 849.281 ; gain = 678.648 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:02:16 ; elapsed = 10:30:30 . Memory (MB): peak = 849.281 ; gain = 678.648 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Completed Processing XDC Constraints INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. RTL Elaboration Complete: : Time (s): cpu = 00:02:32 ; elapsed = 10:30:40 . Memory (MB): peak = 1120.141 ; gain = 949.508 14 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:16 . Memory (MB): peak = 1120.141 ; gain = 279.566 open_run synth_1 -name synth_1 Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7a100tcsg324-1 INFO: [Project 1-479] Netlist was created with Vivado 2015.4 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. CRITICAL WARNING: [Chipscope 16-3] Cannot debug net 'NEXT_ZERO'; it is not accessible from the fabric routing. reset_run synth_1 launch_runs synth_1 INFO: [HDL 9-2216] Analyzing Verilog file "C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v" into library work [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:1] [Tue Jun 07 11:05:44 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.runs/synth_1/runme.log refresh_design INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2015.4 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). refresh_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 1651.500 ; gain = 0.000 reset_run synth_1 launch_runs synth_1 INFO: [HDL 9-2216] Analyzing Verilog file "C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v" into library work [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:1] [Tue Jun 07 11:06:41 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.runs/synth_1/runme.log close_design refresh_design --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:04:35 ; elapsed = 10:39:40 . Memory (MB): peak = 1651.500 ; gain = 1480.867 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'latch' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:23] Parameter WIDTH bound to: 8 - type: integer Parameter NUM bound to: 256 - type: integer INFO: [Synth 8-638] synthesizing module 'alu_cir' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:79] Parameter ALU_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'alu_cir' (1#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:79] INFO: [Synth 8-638] synthesizing module 'mux2t1' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:56] Parameter MUX_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'mux2t1' (2#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:56] INFO: [Synth 8-638] synthesizing module 'Register' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:69] Parameter R_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'Register' (3#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:69] INFO: [Synth 8-638] synthesizing module 'Memory' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:39] Parameter M_WIDTH bound to: 8 - type: integer Parameter M_HEIGHT bound to: 256 - type: integer INFO: [Synth 8-256] done synthesizing module 'Memory' (4#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:39] WARNING: [Synth 8-3848] Net NEXT_ZERO in module/entity latch does not have driver. [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:27] INFO: [Synth 8-256] done synthesizing module 'latch' (5#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:23] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:04:36 ; elapsed = 10:39:41 . Memory (MB): peak = 1651.500 ; gain = 1480.867 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:04:36 ; elapsed = 10:39:41 . Memory (MB): peak = 1651.500 ; gain = 1480.867 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-141] Inserted 64 OBUFs to IO ports without IO buffers. Processing XDC Constraints Initializing timing engine Completed Processing XDC Constraints INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). refresh_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 1651.500 ; gain = 0.000 open_run synth_1 -name synth_1 Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7a100tcsg324-1 INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2015.4 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. reset_run synth_1 launch_runs synth_1 INFO: [HDL 9-2216] Analyzing Verilog file "C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v" into library work [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:1] [Tue Jun 07 11:13:23 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.runs/synth_1/runme.log refresh_design INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2015.4 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). refresh_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 1682.078 ; gain = 0.000 close_design close_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1686.516 ; gain = 4.438 close_design open_run synth_1 -name synth_1 Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7a100tcsg324-1 INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2015.4 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. close_design reset_run synth_1 launch_runs synth_1 INFO: [HDL 9-2216] Analyzing Verilog file "C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v" into library work [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:1] [Tue Jun 07 11:20:20 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.runs/synth_1/runme.log open_run synth_1 -name synth_1 Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7a100tcsg324-1 INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2015.4 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. synth_design -rtl -name rtl_1 Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xc7a100tcsg324-1 Top: latch --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:08:08 ; elapsed = 10:58:20 . Memory (MB): peak = 1686.516 ; gain = 1515.883 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'latch' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:23] Parameter WIDTH bound to: 8 - type: integer Parameter NUM bound to: 256 - type: integer INFO: [Synth 8-638] synthesizing module 'alu_cir' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:78] Parameter ALU_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'alu_cir' (1#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:78] INFO: [Synth 8-638] synthesizing module 'mux2t1' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:55] Parameter MUX_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'mux2t1' (2#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:55] INFO: [Synth 8-638] synthesizing module 'Register' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:68] Parameter R_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'Register' (3#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:68] INFO: [Synth 8-638] synthesizing module 'Memory' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:38] Parameter M_WIDTH bound to: 8 - type: integer Parameter M_HEIGHT bound to: 256 - type: integer INFO: [Synth 8-256] done synthesizing module 'Memory' (4#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:38] WARNING: [Synth 8-3848] Net NEXT_ZERO in module/entity latch does not have driver. [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:27] INFO: [Synth 8-256] done synthesizing module 'latch' (5#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:23] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO[7] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO[6] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO[5] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO[4] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO[3] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO[2] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO[1] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO[0] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:08:09 ; elapsed = 10:58:21 . Memory (MB): peak = 1686.516 ; gain = 1515.883 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:08:10 ; elapsed = 10:58:21 . Memory (MB): peak = 1686.516 ; gain = 1515.883 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-141] Inserted 64 OBUFs to IO ports without IO buffers. Processing XDC Constraints Initializing timing engine Completed Processing XDC Constraints INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. RTL Elaboration Complete: : Time (s): cpu = 00:08:16 ; elapsed = 10:58:25 . Memory (MB): peak = 1738.316 ; gain = 1567.684 14 Infos, 9 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 1738.316 ; gain = 51.801 close_design close_design synth_design -rtl -name rtl_1 Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xc7a100tcsg324-1 Top: latch --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:08:40 ; elapsed = 11:00:26 . Memory (MB): peak = 1738.316 ; gain = 1567.684 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'latch' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:23] Parameter WIDTH bound to: 8 - type: integer Parameter NUM bound to: 256 - type: integer INFO: [Synth 8-638] synthesizing module 'alu_cir' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:78] Parameter ALU_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'alu_cir' (1#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:78] INFO: [Synth 8-638] synthesizing module 'mux2t1' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:55] Parameter MUX_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'mux2t1' (2#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:55] INFO: [Synth 8-638] synthesizing module 'Register' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:68] Parameter R_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'Register' (3#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:68] INFO: [Synth 8-638] synthesizing module 'Memory' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:38] Parameter M_WIDTH bound to: 8 - type: integer Parameter M_HEIGHT bound to: 256 - type: integer INFO: [Synth 8-256] done synthesizing module 'Memory' (4#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:38] WARNING: [Synth 8-3848] Net NEXT_ZERO in module/entity latch does not have driver. [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:27] INFO: [Synth 8-256] done synthesizing module 'latch' (5#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:23] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO[7] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO[6] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO[5] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO[4] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO[3] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO[2] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO[1] WARNING: [Synth 8-3331] design latch has unconnected port NEXT_ZERO[0] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:08:41 ; elapsed = 11:00:27 . Memory (MB): peak = 1738.316 ; gain = 1567.684 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:08:42 ; elapsed = 11:00:27 . Memory (MB): peak = 1738.316 ; gain = 1567.684 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-141] Inserted 64 OBUFs to IO ports without IO buffers. Processing XDC Constraints Initializing timing engine Completed Processing XDC Constraints INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. RTL Elaboration Complete: : Time (s): cpu = 00:08:48 ; elapsed = 11:00:31 . Memory (MB): peak = 1738.316 ; gain = 1567.684 14 Infos, 9 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:09 . Memory (MB): peak = 1738.316 ; gain = 0.000 close_design synth_design -rtl -name rtl_1 Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xc7a100tcsg324-1 Top: latch ERROR: [Synth 8-2715] syntax error near endmodule [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:37] ERROR: [Synth 8-2537] port ROM_addr is not defined [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:42] ERROR: [Synth 8-2537] port ROM_data is not defined [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:43] INFO: [Synth 8-2350] module latch ignored due to previous errors [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:23] INFO: [Synth 8-2350] module mux2t1 ignored due to previous errors [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:56] INFO: [Synth 8-2350] module Register ignored due to previous errors [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:69] INFO: [Synth 8-2350] module alu_cir ignored due to previous errors [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:79] INFO: [Synth 8-2350] module CMPer ignored due to previous errors [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:88] Failed to read verilog 'C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v' 5 Infos, 0 Warnings, 0 Critical Warnings and 4 Errors encountered. synth_design failed ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details reset_run synth_1 launch_runs synth_1 INFO: [HDL 9-2216] Analyzing Verilog file "C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v" into library work [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:1] CRITICAL WARNING: [HDL 9-806] Syntax error near "endmodule". [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:37] [Tue Jun 07 11:30:39 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.runs/synth_1/runme.log reset_run synth_1 launch_runs synth_1 INFO: [HDL 9-2216] Analyzing Verilog file "C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v" into library work [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:1] [Tue Jun 07 11:31:41 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.runs/synth_1/runme.log open_run synth_1 -name synth_1 Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7a100tcsg324-1 INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2015.4 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. synth_design -rtl -name rtl_1 Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xc7a100tcsg324-1 Top: latch --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:09:47 ; elapsed = 11:05:02 . Memory (MB): peak = 1738.316 ; gain = 1567.684 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'latch' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:23] Parameter WIDTH bound to: 8 - type: integer Parameter NUM bound to: 256 - type: integer INFO: [Synth 8-638] synthesizing module 'alu_cir' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:79] Parameter ALU_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'alu_cir' (1#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:79] INFO: [Synth 8-638] synthesizing module 'mux2t1' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:56] Parameter MUX_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'mux2t1' (2#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:56] INFO: [Synth 8-638] synthesizing module 'Register' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:69] Parameter R_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'Register' (3#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:69] INFO: [Synth 8-638] synthesizing module 'Memory' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:39] Parameter M_WIDTH bound to: 8 - type: integer Parameter M_HEIGHT bound to: 256 - type: integer INFO: [Synth 8-256] done synthesizing module 'Memory' (4#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:39] INFO: [Synth 8-638] synthesizing module 'CMPer' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:88] Parameter CMP_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'CMPer' (5#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:88] WARNING: [Synth 8-689] width (8) of port connection 'out' does not match port width (1) of module 'CMPer' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:36] INFO: [Synth 8-256] done synthesizing module 'latch' (6#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:23] WARNING: [Synth 8-3917] design latch has port NEXT_ZERO[7] driven by constant 0 WARNING: [Synth 8-3917] design latch has port NEXT_ZERO[6] driven by constant 0 WARNING: [Synth 8-3917] design latch has port NEXT_ZERO[5] driven by constant 0 WARNING: [Synth 8-3917] design latch has port NEXT_ZERO[4] driven by constant 0 WARNING: [Synth 8-3917] design latch has port NEXT_ZERO[3] driven by constant 0 WARNING: [Synth 8-3917] design latch has port NEXT_ZERO[2] driven by constant 0 WARNING: [Synth 8-3917] design latch has port NEXT_ZERO[1] driven by constant 0 --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:09:48 ; elapsed = 11:05:03 . Memory (MB): peak = 1738.316 ; gain = 1567.684 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:09:49 ; elapsed = 11:05:03 . Memory (MB): peak = 1738.316 ; gain = 1567.684 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-141] Inserted 72 OBUFs to IO ports without IO buffers. Processing XDC Constraints Initializing timing engine Completed Processing XDC Constraints INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. RTL Elaboration Complete: : Time (s): cpu = 00:09:55 ; elapsed = 11:05:07 . Memory (MB): peak = 1756.293 ; gain = 1585.660 16 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 1756.293 ; gain = 17.977 close_design close_design synth_design -rtl -name rtl_1 Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xc7a100tcsg324-1 Top: latch --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:10:08 ; elapsed = 11:05:58 . Memory (MB): peak = 1756.293 ; gain = 1585.660 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'latch' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:23] Parameter WIDTH bound to: 8 - type: integer Parameter NUM bound to: 256 - type: integer INFO: [Synth 8-638] synthesizing module 'alu_cir' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:79] Parameter ALU_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'alu_cir' (1#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:79] INFO: [Synth 8-638] synthesizing module 'mux2t1' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:56] Parameter MUX_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'mux2t1' (2#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:56] INFO: [Synth 8-638] synthesizing module 'Register' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:69] Parameter R_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'Register' (3#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:69] INFO: [Synth 8-638] synthesizing module 'Memory' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:39] Parameter M_WIDTH bound to: 8 - type: integer Parameter M_HEIGHT bound to: 256 - type: integer INFO: [Synth 8-256] done synthesizing module 'Memory' (4#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:39] INFO: [Synth 8-638] synthesizing module 'CMPer' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:88] Parameter CMP_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'CMPer' (5#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:88] WARNING: [Synth 8-689] width (8) of port connection 'out' does not match port width (1) of module 'CMPer' [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:36] INFO: [Synth 8-256] done synthesizing module 'latch' (6#1) [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:23] WARNING: [Synth 8-3917] design latch has port NEXT_ZERO[7] driven by constant 0 WARNING: [Synth 8-3917] design latch has port NEXT_ZERO[6] driven by constant 0 WARNING: [Synth 8-3917] design latch has port NEXT_ZERO[5] driven by constant 0 WARNING: [Synth 8-3917] design latch has port NEXT_ZERO[4] driven by constant 0 WARNING: [Synth 8-3917] design latch has port NEXT_ZERO[3] driven by constant 0 WARNING: [Synth 8-3917] design latch has port NEXT_ZERO[2] driven by constant 0 WARNING: [Synth 8-3917] design latch has port NEXT_ZERO[1] driven by constant 0 --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:10:09 ; elapsed = 11:05:59 . Memory (MB): peak = 1756.293 ; gain = 1585.660 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:10:10 ; elapsed = 11:05:59 . Memory (MB): peak = 1756.293 ; gain = 1585.660 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-141] Inserted 72 OBUFs to IO ports without IO buffers. Processing XDC Constraints Initializing timing engine Completed Processing XDC Constraints INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. RTL Elaboration Complete: : Time (s): cpu = 00:10:16 ; elapsed = 11:06:03 . Memory (MB): peak = 1756.293 ; gain = 1585.660 16 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:09 . Memory (MB): peak = 1756.293 ; gain = 0.000 open_run synth_1 -name synth_1 Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7a100tcsg324-1 INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2015.4 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. close_design open_run synth_1 -name synth_1 Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7a100tcsg324-1 INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2015.4 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. close_design close_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1756.293 ; gain = 0.000 close_design reset_run synth_1 launch_runs synth_1 INFO: [HDL 9-2216] Analyzing Verilog file "C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v" into library work [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:1] [Tue Jun 07 11:41:06 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.runs/synth_1/runme.log open_run synth_1 -name synth_1 Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7a100tcsg324-1 INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2015.4 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. close_design reset_run synth_1 launch_runs synth_1 INFO: [HDL 9-2216] Analyzing Verilog file "C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v" into library work [C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.srcs/sources_1/new/exp4_2.v:1] [Tue Jun 07 11:44:17 2016] Launched synth_1... Run output will be captured here: C:/Users/Rongren/Downloads/verilog_exp/exp4_2/exp_2.runs/synth_1/runme.log open_run synth_1 -name synth_1 Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7a100tcsg324-1 INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2015.4 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. exit INFO: [Common 17-206] Exiting Vivado at Tue Jun 07 13:11:44 2016...