*** Running vivado with args -log full_add.vds -m64 -mode batch -messageDb vivado.pb -notrace -source full_add.tcl ****** Vivado v2015.2 (64-bit) **** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015 **** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015 ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. source full_add.tcl -notrace Command: synth_design -top full_add -part xc7a100tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-1223] The version limit for your license is '2016.05' and will expire in 4 days. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 262.676 ; gain = 49.879 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'full_add' [D:/exp_sub/exp_sub.srcs/sources_1/new/full_add.v:23] INFO: [Synth 8-256] done synthesizing module 'full_add' (1#1) [D:/exp_sub/exp_sub.srcs/sources_1/new/full_add.v:23] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 297.012 ; gain = 84.215 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 297.012 ; gain = 84.215 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 INFO: [Device 21-403] Loading part xc7a100tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 297.012 ; gain = 84.215 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 304.148 ; gain = 91.352 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module full_add Detailed RTL Component Info : +---XORs : 3 Input 1 Bit XORs := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Start Parallel Synthesis Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 438.695 ; gain = 225.898 --------------------------------------------------------------------------------- Start Cross Boundary Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 438.695 ; gain = 225.898 --------------------------------------------------------------------------------- Finished Parallel Reinference : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 438.695 ; gain = 225.898 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 448.055 ; gain = 235.258 --------------------------------------------------------------------------------- Finished Parallel Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 448.055 ; gain = 235.258 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Finished Parallel Synthesis Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 448.055 ; gain = 235.258 --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 448.055 ; gain = 235.258 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 448.055 ; gain = 235.258 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 448.055 ; gain = 235.258 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 448.055 ; gain = 235.258 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 448.055 ; gain = 235.258 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 448.055 ; gain = 235.258 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 448.055 ; gain = 235.258 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |LUT3 | 1| |2 |LUT4 | 1| |3 |IBUF | 4| |4 |OBUF | 2| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 8| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 448.055 ; gain = 235.258 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 448.055 ; gain = 216.551 Synthesis Optimization Complete : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 448.055 ; gain = 235.258 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 515.875 ; gain = 293.664 report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.167 . Memory (MB): peak = 515.875 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Fri May 27 20:01:36 2016...